1. Field of the Invention
The invention relates to the field of dielectric layers employed within microelectronics fabrications. More particularly, the invention relates to the field of delamination resistant dielectric layers employed for passivation of microelectronics fabrications.
2. Description of the Related Art.
As the dimensions of microelectronics fabrications have decreased, the sensitivity of such devices to environmental factors has required that the methods for passivation and protection of microelectronics fabrications be improved. Microelectronics fabrications are passivated and protected primarily by insuring that the surfaces of the fabrications be covered and sealed with impervious coatings of chemically and physically stable materials, and secondarily by placing the completed fabrication with its attendant electrical leads and connections within another protective enclosure or "package" so that the device may be handled and employed as designed with reasonable security from any potentially harmful environment. To insure adequate protection, the protective structures must be inherently free from porosity and their fabrication must insure freedom from cracks or defects at joints, interfaces and seams.
The primary passivation of microelectronics fabrications, particularly those employing semiconductor materials which are especially sensitive to extremely small chemical or physical changes at their surfaces, is generally achieved by forming individual or composite surface layers of silicon containing dielectric materials such as silicon oxide or silicon nitride because of the excellent physical and chemical stability of these materials and their relative ease of formation and methods of shaping. The secondary protective methods, or packaging, of microelectronics fabrications generally employ thermoplastic or thermosetting organic polymer materials molded as overcoating layers around the microelectronics fabrication with its attendant attached leads and connections. This method is particularly widely employed in situations where manufacturing cost is an important factor and environmental conditions for use of the device are not very severe.
Although satisfactory methods of passivation with silicon containing dielectric materials and packaging with molded organic polymer materials are available for microelectronics fabrications, these methods of protecting microelectronics fabrications are not without problems. In particular, composite silicon containing dielectric layers and molded organic polymer materials formed around devices coated with silicon containing passivation layers often experience difficulties due to poor adhesion of the molded organic polymer material to surfaces typical of silicon containing dielectric layers, as well as delamination between the composite layers.
It is towards the goal of providing enhanced adhesion of protective layers and coatings to microelectronics fabrications that the present invention is generally and more specifically directed.
Various methods have been disclosed for forming passivation layers and protective packaging enclosures upon microelectronics fabrications.
For example, Jain, in U.S. Pat. No. 5,494,854, discloses a method for forming a planarized dielectric passivation layer upon a patterned layer semiconductor microelectronics fabrication. The method first forms a gap filling silicon oxide dielectric layer by high density plasma chemical vapor deposition, followed by a second silicon oxide dielectric layer formed by plasma enhanced chemical vapor deposition and subsequent chemical mechanical polish (CMP) planarization.
Further, Berg et al., in U.S. Pat. No. 5,756,380, disclose a method for forming a moisture resistant microelectronics fabrication employing an organic substrate which is resistant to delamination or cracking at interfaces. The method employs organic polymer materials for attachment of the microelectronics fabrication to the substrate and for overall encapsulation.
Still further, Lou, in U.S. Pat. No. 5,759,906, discloses a method for forming a planarized inter-level metal dielectric (IMD) layer with via contact holes on integrated circuit microelectronics fabrications. The method employs combinations of dielectric layers formed employing plasma enhanced chemical vapor deposition (PECVD) and low dielectric constant dielectric layers formed from spin-on-glass (SOG) dielectric materials as well as chemical mechanical polish (CMP) planarization to realize the planar inter-level metal dielectric (IMD) layer. Multiple baking steps between fabrication of layers is employed to minimize via contact hole poisoning.
Yet still further, Robles, in U.S. Pat. No. 5,804,259, discloses a method for forming a multi-layer low dielectric constant dielectric layer on a substrate. The method employs forming a first layer of carbonaceous diamond-like dielectric material followed by layers of organic polymer dielectric materials such as poly-p-xylylene (Parylene) to form a composite low dielectric constant dielectric layer.
Finally, Shin, in U.S. Pat. No. 5,807,768, discloses a method for forming a package of molded epoxy resin to encapsulate a semiconductor integrated circuit microelectronics fabrication and integral heat sink. The molded package is fabricated in two parts, the first being of greater bonding strength than the second, to afford greater resistance to delamination at the interface between the first molded part and the integrated circuit microelectronics fabrication integral heat sink combination.
Desirable in the art of microelectronics fabrication are additional methods and materials for forming passivation layers and molded organic polymer package structures with improved resistance to delamination or other structural failure modes.
It is towards these goals that the present invention is generally and specifically directed.